The present invention relates to a semiconductor integrated circuit device and, more particularly, to improvements applied advantageously to a semiconductor integrated circuit device having an SRAM (static random access memory).
Recently, efforts have been made at various institutions to develop SRAMs having as large as 1 to 4 megabits of memory capacity. The design rules being applied envisage carrying out fabrication to about 0.4 .mu.m.
As shown in FIG. 44, the general SRAM chip layout is composed of memory cell arrays for holding data. At the periphery of the memory cell arrays are word drivers, pre-decoders and Y-switches, i.e., direct peripheral circuits that select appropriate memory cells when data is written or read thereto or therefrom. These circuits are, in turn, surrounded by input and output buffers, i.e., peripheral circuits for controlling actual circuit operations. In the description that follows, the direct peripheral circuits and their associated peripheral circuits will be referred to simply as peripheral circuits.
The memory cells in the above-mentioned memory cell arrays are of one of two types: high resistance load type, and complete CMOS (complementary metal oxide semiconductor) type. The high resistance load type memory cell combines resistor elements with n-channel MISFETs (metal insulator semiconductor field effect transistors); the complete CMOS type memory cell combines n-channel MISFETs with p-channel MISFETs. These memory cells are designed for high degrees of integration and high yield in fabrication.
The so-called CMOS SRAM is used as the main memory for systems for which low costs are emphasized, such as mainframe computers and workstations. The CMOS SRAM combines high resistance load type or complete CMOS type memory cells with peripheral circuits composed of MISFETs. For the mainframe computers and workstations to operate at high speed, it is necessary to have a cache memory outside their main memory, the cache accommodating data temporarily for fast access thereto. The cache memory is made up of what is known as a bipolar CMOS SRAM. The bipolar CMOS SRAM combines high resistance load type or complete CMOS type memory cells with peripheral circuits composed of bipolar transistors and CMOSFETs. The SRAM is discussed illustratively in IEDM (International Electron Device Meeting), Tech. Dig., pp. 447-480, 1991.
As depicted in FIG. 45, a high resistance load type memory cell of the SRAM typically comprises a pair of driver MISFETs Qd.sub.1 and Qd.sub.2, a pair of resistor elements (load elements) R1 and R2, a pair of transistor MISFETs Qt.sub.1 and Qt.sub.2, a pair of complementary data lines (DL, bar DL), and a pair of word lines WL.sub.1 and WL.sub.2. The driver MISFETs Qd.sub.1 and Qd.sub.2 as well as the transfer MISFETs Qt.sub.1 and Qt.sub.2 are an n-channel MISFET each.
The two driver MISFETs Qd.sub.1 and Qd.sub.2 and the pair of resistor elements R.sub.1 and R.sub.2 constitute a flip-flop circuit that acts as a data storage part. That is, when both transfer MISFETs Qt.sub.1 and Qt.sub.2 are off, this storage part stores one-bit data by stabilizing in one of two states. In one state, a storage node A (one of two I/O terminals of the flip-flop circuit) is at the high potential level while a storage node B (the other of the two I/O terminals) is at the low potential level (at this point, the driver MISFET Qd.sub.1 is turned off, preventing currents from flowing through the resistor element R.sub.1 ; the driver MISFET Qd.sub.2 is turned on, allowing a holding current to flow through the resistor element R.sub.2). In the other state in which the data storage part is stabilized to retain one-bit data, the storage node A is at the low potential level while the storage node B is at the high potential level (at this point, the driver MISFET Qd.sub.1 is turned on, allowing the holding current to flow through the resistor element R.sub.1 ; the driver MISFET Qd.sub.2 is turned off, preventing currents from flowing through the resistor element R.sub.2).
To write data to the above memory cell requires setting the word lines WL.sub.1 and WL.sub.2 at the high potential level and turning on the transfer MISFETs Qt.sub.1 and Qt.sub.2. This causes the data on the data lines DL and bar DL to be transmitted to the storage nodes A and B. To read data from the memory cell involves setting the word lines WL.sub.1 and WL.sub.2 at the high potential level and turning on the transfer MISFETs Qt.sub.1 and Qt.sub.2. This transmits the data on the storage nodes A and B to the data lines DL and bar DL.
In the memory cell, a pn junction capacitance (Cpn.sub.1) and a gate capacitance (Cox.sub.1) shown in FIG. 45 are generated between the storage node A and the substrate (p-type semiconductor substrate or p-type well). Thus when the storage node A is illustratively at the high potential level, the pn junction capacitance (Cpn.sub.1) and gate capacitance (Cox.sub.1) are charged electrically. The greater the pn junction capacitance (Cpn.sub.1) and the gate capacity (Cox.sub.1), the more stable the high potential level held in the storage node A. Likewise, another pn junction capacitance (Cpn.sub.2) and another gate capacitance (Cox.sub.2) are formed between the storage node B and the substrate. In the latter case, too, the greater the capacitances, the more stable the high potential level held in the storage node B.
FIG. 46 is a plan view of a typical layout pattern including active regions 50, gate electrodes 51 of the driver MISFETs Qd.sub.1 and Qd.sub.2, gate electrodes 52 (word lines WL.sub.1 and WL.sub.2) of the transfer MISFETs Qt.sub.1 and Qt.sub.2 in a memory cell formed on the semiconductor substrate. The driver MISFETs Qd.sub.1 and Qd.sub.2, transfer MISFETs Qt.sub.1 and Qt.sub.2, storage nodes A and B, and word lines WL.sub.1 and WL.sub.2 correspond to their counterpart circuits in FIG. 45.
FIG. 47A is a plan view schematically showing the gate capacitances (Cox) in effect when the storage node A of the memory cell is at the high potential level. As illustrated, the gate capacity (Cox.sub.2) of the driver MISFET Qd.sub.2 being turned on comprises two components: one formed in a channel forming region (indicated by hatching pattern), the other in a capacitance-dedicated region (indicated by shadow pattern). The gate capacitance (Cox.sub.1) of the driver MISFET Qd.sub.1 being turned off is generated in the overlapping area between the gate electrode and the drain region (indicated by hatching pattern).
As shown in FIG. 47A, one edge of each of the gate electrodes 51 for the driver MISFETs Qd.sub.1 and Qd.sub.2 extends in the direction of a field insulating film. The electrode extension corresponds to an allowance (x) for mask alignment provided when the gate electrodes 51 are formed by etching a conductive layer deposited on the semiconductor substrate. As will be explained later, too small allowance (x) for mask alignment would leave the edges of the gate electrodes 51 shrunk toward the active regions 50. Should this occur, the drain and source regions would come too close to each other at the edge of each active region 50, thereby making it difficult to ward off leaks therebetween and to retain data stably.
The high resistance load type memory cell mentioned above is fabricated illustratively in the process to be described below. Of the figures (FIGS. 48 through 67) showing how the memory cell is fabricated, the plan views give only the conductive layers of the cell and not the insulating layer between these layers.
As shown in FIG. 48, FIG. 49 (cross-sectional view taken on line A-A' in FIG. 48) and FIG. 50 (cross-sectional view taken on line B-B' in FIG. 48), a field insulating film 55 is first formed illustratively by the LOCOS (localized oxidation of silicon) method on a p-type well 54 over a p-type semiconductor substrate 53 made of silicon single crystal. After the field insulating film 55 is formed, a gate insulating film 56 is deposited on the surface of the active regions 50 surrounded by the field insulating film 55.
Next, a first layer polycrystal silicon film deposited on the semiconductor substrate 53 is patterned by optical lithography and etching techniques into the gate electrodes 51 of the driver MISFETs Qd.sub.1 and Qd.sub.2 and the gate electrodes 52 (word lines WL.sub.1 and WL.sub.2) of the transfer MISFETs Qt.sub.1 and Qt.sub.2. After the gate electrodes 51 and 52 are formed, they are used as the mask with which n-type impurity ions (e.g., phosphorus (P)) are implanted into the semiconductor substrate 53. This produces n.sup.- type semiconductor regions 57 of low impurity density. The n.sup.- type semiconductor regions 57 constitute part of the source and drain regions of the driver MISFETs Qd.sub.1 and Qd.sub.2, and part of the source and drain regions of the transfer MISFETs Qt.sub.1 and Qt.sub.2.
Then as shown in FIGS. 51 and 52, a silicon oxide film deposited on the semiconductor substrate 53 is etched anisotropically into side wall spacers 58 of the side walls for both the gate electrodes 51 of the driver MISFETs Qd.sub.1 and Qd.sub.2 and the gate electrodes 52 (word lines WL.sub.1 and WL.sub.2) of the transfer MISFETs Qt.sub.1 and Qt.sub.2. With the side wall spacers 58 thus formed, the gate electrodes 51 and 52 and the side wall spacers 58 are used as the mask with which n-type impurity ions (such as arsenic (As)) are implanted into the semiconductor substrate 53. This produces n.sup.+ type semiconductor regions 59 of high impurity density. The n.sup.+ type semiconductor regions 59 constitute part of the source and drain regions for the driver MISFETs Qd.sub.1 and Qd.sub.2, and part of the source and drain regions for the transfer MISFETs Qt.sub.1 and Qt.sub.2.
Then as shown in FIG. 53, FIG. 54 (cross-sectional view taken on line A-A' in FIG. 53) and FIG. 55 (cross-sectional view taken on line B-B' in FIG. 53), a silicon oxide film 60 is deposited on the semiconductor substrate 53 so as to form connecting holes 61, 62 and 63 spanning the n.sup.+ type semiconductor regions 59 and the gate electrodes 51 of the driver MISFETs Qd.sub.1 and Qd.sub.2. After this, a second layer polycrystal silicon film 64 is deposited on the silicon oxide film 60. This film is patterned into the plane layout shown in FIG. 57.
Thereafter, as shown in FIG. 56, FIG. 57 (cross-sectional view taken on line A-A' in FIG. 56) and FIG. 58 (cross-sectional view taken on line B-B' in FIG. 56), a photo resist film 65 is used as the mask with which n-type impurity ions (phosphorus (P), arsenic (As), antimony (Sb), etc.) are implanted into part of the polycrystal silicon film 64. The ion implantation splits the polycrystal silicon film 64 into low-resistance wiring 64A, pad layers 64B and 64C, and resistor elements R.sub.1 and R.sub.2, as depicted in FIG. 59, FIG. 60 (cross-sectional view taken on line A-A' in FIG. 59), and FIG. 61 (cross-sectional view taken on line B-B' in FIG. 59).
One end of each of the resistor elements R.sub.1 and R.sub.2 is supplied with a circuit power source voltage Vcc via the wiring 64A. The other end of each of the resistor elements R.sub.1 and R.sub.2 is connected via connecting holes 63 both to the drain regions (n.sup.+ type semiconductor regions 59) on one side of the driver MISFETs Qd.sub.1 and Qd.sub.2, and to the gate electrodes 51 on the other side thereof. In this manner, the high resistance load type memory cell is made smaller than ever by locating the resistor elements R.sub.1 and R.sub.2 in the layer above the driver MISFETs Qd.sub.1 and Qd.sub.2.
Then as shown in FIG. 62, FIG. 63 (cross-sectional view taken on line A-A' in FIG. 62) and FIG. 64 (cross-sectional view taken on line B-B' in FIG. 62), a first layer insulating film 66 is deposited on top of the wiring 64A, the pad layers 64B and 64C, and the resistor elements R.sub.1 and R.sub.2. This produces connecting holes 67 reaching the pad layer 64B and connecting holes 68 reaching the pad layer 64C. With the connecting holes produced, a first layer aluminum (Al) film is deposited over the layer insulating film 66, and is patterned into wiring 69A, a pad layer 69B and word shunts 69C. The wiring 69A is connected to the source regions (n.sup.+ type semiconductor regions 59) of the driver MISFETs Qd.sub.1 and Qd.sub.2 via the connecting holes 68, pad layer 64C and connecting holes 62. The source regions are in turn connected via the wiring 69A to a circuit reference voltage Vss. The word shunts 69C are connected to the word lines WL.sub.1 and WL.sub.2 via connecting holes formed in regions, not shown, of the layer insulating film 66. For the ease of viewing, FIG. 62 omits showing the active regions, the gate electrodes 51 of the driver MISFETs Qd.sub.1 and Qd.sub.2, and the gate electrodes 52 (word lines WL.sub.1 and WL.sub.2) of the transfer MISFETs Qt.sub.1 and Qt.sub.2.
Then as shown in FIG. 65, FIG. 66 (cross-sectional view taken on line A-A' in FIG. 65) and FIG. 67 (cross-sectional view taken on line B-B' in FIG. 65), a second layer insulating film 70 is deposited on top of the wiring 69A, the pad layer 69B, and the word shunts 69C. This produces connecting holes 71 reaching the pad layer 69B. With the connecting holes 71 produced, a second layer aluminum (Al) film is deposited over the layer insulating film 70, and is patterned into the data lines (DL, bar DL). For the ease of viewing, FIG. 65 omits showing the active regions, the gate electrodes 51 of the driver MISFETs Qd.sub.1 and Qd.sub.2, the gate electrodes 52 (word lines WL.sub.1 and WL.sub.2) of the transfer MISFETs Qt.sub.1 and Qt.sub.2, the wiring layer 64A, the pad layers 64B and 64C, and the resistor elements R.sub.1 and R.sub.2.
The data line (DL) is connected to the drain regions (n.sup.+ type semiconductor regions 59) of the transfer MISFET Qt.sub.2 via the connecting holes 71, pad layer 69B, connecting holes 67, pad layer 64B and connecting holes 61. The data line (bar DL) is connected to the drain regions (n.sup.+ type semiconductor regions 59) of the transfer MISFET Qt.sub.1 via the connecting holes 71, pad layer 69B, connecting holes 67, pad layer 64B and connecting holes 61. After this, a final passivation film 72 is deposited over the data lines (DL, bar DL), whereby the high resistance load type memory cell is completed.
Suppose that the above-described memory cell of a dual-layer polycrystal silicon film, dual-layer aluminum wiring structure is to be designed illustratively under rules on fabrication to 0.4 .mu.m. In that case, the source and drain regions (n.sup.+ type semiconductor regions 59) of the driver MISFETs Qd.sub.1 and Qd.sub.2 and of the transfer MISFETs Qt.sub.1 and Qt.sub.2 need to be 0.15 .mu.m in junction depth.
In the above process where the first layer insulating film 66 is etched to form the connecting holes 68 for connecting the first layer aluminum wiring (wiring 69A) with the second layer polycrystal silicon film (pad layer 64C), the second layer polycrystal silicon film (pad layer 64C) under the layer insulating film 66 is etched by about 0.1 .mu.m through over-etching action. Since the wiring 69A made of aluminum has the p-type conductivity, an attempt to connect the wiring 69A to the source regions (n.sup.+ type semiconductor regions 59) of the driver MISFETs Qd.sub.1 and Qd.sub.2 without the intermediary of the pad layer 64C can result in leaks or short-circuits between the wiring 69A and the p-type well 54 under the shallow n.sup.+ type semiconductor regions 59. With that taken into account, it is indispensable to form the pad layer 64C using the second layer polycrystal silicon film.
As described, where the above-described memory cell of the dual-layer polycrystal silicon film, dual-layer aluminum wiring structure is designed illustratively under rules on fabrication to about 0.4 .mu.m, the memory cell size is determined by two factors. One of the two determining factors is the accuracy in fabricating the second layer polycrystal silicon film constituting the wiring layer 64A, pad layer 64B and 64C, and resistor elements R.sub.1 and R.sub.2. The other factor that determines the memory cell size is the accuracy of photo resist film alignment in effect when impurity ions are implanted into the second layer polycrystal silicon film (see FIGS. 56 to 58).